This application claims the priority benefit of Taiwan application Ser. No. 89119794, filed Sep. 26, 2000.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a high voltage device that raises the breakdown voltage.
2. Description of the Related Art
Recently, the goal in the development of the semiconductor industry is to increase the integration of the integrated circuit. However, when the device is gradually reduced in size, the breakdown voltage also decreases correspondingly. Therefore, in the design of a semiconductor high voltage device, raising of the breakdown voltage must be considered. Generally, the integrated circuit device includes some high voltage devices, such as an electrically programmable read-only memory (EPROM) or a flash memory.
In the semiconductor processing of the related art, in order to increase the breakdown voltage of the junction between a MOSFET (metal oxide semiconductor field effect transistor) and a well, usually a lightly doped offset region is added surrounding the source/drain region, in order to raise the junction breakdown voltage.
FIGS. 1A and 1B are flow diagrams in cross-sectional view illustrating a method of manufacturing high voltage device. Referring to FIG. 1A, a P-type substrate 100 is provided. By using an ion implantation process, a doped implanted substrate required by the P-well 102 is formed, and a gate structure 110 made up of a gate oxide layer 104, a gate 106, and an optional cap layer 108 are formed over the P-well in sequence.
Referring to FIG. 1B, by using the gate structure 110 as a mask, an Nxe2x88x92 ion implantation procedure is performed on the high voltage device region of the P-well 102, thereby forming lightly doped regions 112a and 112b. 
Referring to FIG. 1C, a spacer 114 is formed on the sidewall of the gate structure 110. Next, an offset mask 116 is formed on the P-well 102. Subsequently, by using the offset mask 116 as an implantation mask, an N+ ion implantation procedure is performed on the P-well 102, thereby forming source/drain regions 118a and 118b. Directly across from the position of the gate structure, the source/drain regions 118a and 118b move laterally, offsetting the length L. Lightly doped offset regions 112a and 112b are formed around the source/drain regions 118a and 118b. The formation of the lightly doped offset regions 112a and 112b reduces the electric field intensity gradient at the drain region 118 and the P-well 102 junction, thereby raising the breakdown voltage.
With regards to the high voltage metal oxide semiconductors (MOS) field effect transistors (FETs), if there are spaces between the lightly doped offset regions 112a, 112b and the gate 106, then the electric current does not flow easily, and causes an attack on the characteristics of the output current. Consequently, the procedure of forming the lightly doped regions 112a and 112b should prioritize the procedure of forming the spacer 114.
In the manufacturing of the semiconductor high voltage device in the related art, the offset length L is roughly in direct proportion to the breakdown voltage, and the longer the offset length L is, the higher the breakdown voltage is. However, increasing the length of the offset length L causes difficulties in reducing the device size.
The present invention provides a method of manufacturing a high voltage device, to be used to raise the breakdown voltage of the device, enabling the device to withstand high voltage operations, and to meet the requirements of reduced size and increased integration.
As embodied and broadly described herein, the invention provides a method of manufacturing a high voltage device that raises the breakdown voltage. First, a semiconductor substrate with a high voltage device region is provided, and an oxide layer is formed on the semiconductor substrate. Next, a well region is formed on the semiconductor substrate, and the oxide layer is removed. Subsequently, a gate oxide layer is formed on the well region. A gate and an optional cap layer are sequentially formed on the substrate. Hence, the gate oxide layer, the gate and the cap layer together make up the gate structure. Next, a light doping process is performed, wherein the light doping process uses the gate structure as a mask to perform an ion implantation process at a great tilt angle on the high voltage device region of the well region. Thus, a lightly doped region is formed and the lightly doped region extends out to the well region below the gate. After the ion implantation process, an optional process of dopant thermal drive-in is continued, thereby widening the area of the lightly doped region below the gate. Next, a spacer is formed on the sidewall of the gate structure. Subsequently, using the gate structure and the spacer as a mask, a heavy doping process is performed on the well, thereby forming a source/drain region.
According to one method of manufacturing a high voltage device provided in the present invention, the breakdown voltage of the device can be increased, enabling the device to withstand high voltage operations, and simultaneously meeting the requirements of reduced size and increased integration. Moreover, after performing an ion implantation at a large tilt angle, the channel length of the device is effectively reduced, and the device saturation current can be raised, thereby causing the device to operate quickly. There is no offset mask in the process flow of this present invention. Hereby, the cost of the process is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.